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74VCXH16245 Low-Voltage 1.8/2.5/3.3V 16-Bit Transceiver
With 3.6 V-Tolerant Inputs and Outputs (3-State, Non-Inverting)
The 74VCXH16245 is an advanced performance, non-inverting 16-bit transceiver. It is designed for very high-speed, very low-power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be over-voltage tolerant to 3.6 V. The VCXH16245 is designed with byte control. It can be operated as two separate octals, or with the controls tied together, as a 16-bit wide function. The Transmit/Receive (T/Rn) inputs determine the direction of data flow through the bi-directional transceiver. Transmit (active-HIGH) enables data from A ports to B ports; Receive (active-LOW) enables data from B to A ports. The Output Enable inputs (OEn), when HIGH, disable both A and B ports by placing them in a HIGH Z condition. The data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating inputs at a valid logic state.
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48 1
TSSOP-48 DT SUFFIX CASE 1201
MARKING DIAGRAM
48
VCXH16245 AWLYYWW
* Designed for Low Voltage Operation: VCC = 1.65-3.6 V * 3.6 V Tolerant Inputs and Outputs * High Speed Operation: 2.5 ns max for 3.0 to 3.6 V * * * * * * * *
3.0 ns max for 2.3 to 2.7 V 6.0 ns max for 1.65 to 1.95 V Static Drive: 24 mA Drive at 3.0 V 18 mA Drive at 2.3 V 6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal Includes Active Bushold to Hold Unused or Floating Inputs at a Valid Logic State IOFF Specification Guarantees High Impedance When VCC = 0 V* Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 250 mA @ 125C ESD Performance: Human Body Model >2000 V; Machine Model >200 V Pb-Free Package is Available*
1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device 74VCXH16245DT 74VCXH16245DTR 74VCXH16245DTRG Package TSSOP TSSOP Shipping 39 / Rail 2500/Tape & Reel
TSSOP 2500/Tape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
*NOTE: To ensure the outputs activate in the 3-state condition, the output enable pins should be connected to V CC through a pull-up resistor. The value of the resistor is determined by the current sinking capability of the output connected to the OE pin.
(c) Semiconductor Components Industries, LLC, 2004
1
May, 2004 - Rev. 3
Publication Order Number: 74VCXH16245/D
74VCXH16245
T/R1 1 B0 2 B1 3 GND 4 B2 5 B3 6 VCC 7 B4 8 B5 9 GND 10 B6 11 B7 12 B8 13 B9 14 GND 15 B10 16 B11 17 VCC 18 B12 19 B13 20 GND 21 B14 22 B15 23 T/R2 24 48 OE1 47 A0 46 A1 45 GND 44 A2 43 A3 42 VCC 41 A4 40 A5 39 GND 38 A6 37 A7 36 A8 35 A9 34 GND 33 A10 32 A11 31 VCC 30 A12 29 A13 28 GND 27 A14 26 A15 25 OE2 T/R1 48 OE1 25 OE2 24 T/R2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 1 1 1
T/R1
1 48
T/R2
24 25
OE1
OE2
A0:7
B0:7
A8:15
B8:15
One of Eight
Figure 2. Logic Diagram
EN1 EN2 EN3 EN4
1
1
2 3 5 6 8 9 11
2
3
12 13 14 16
Figure 1. 48-Lead Pinout (Top View) PIN NAMES
Pins OEn T/Rn A0-A15 B0-B15 Function Output Enable Inputs Transmit/Receive Inputs Side A Inputs or 3-State Outputs Side B Inputs or 3-State Outputs
4
17 19 20 22 23
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
Figure 3. IEC Logic Diagram
Inputs OE1 L L H T/R1 L H X Outputs O tp ts Bus B0:7 Data to Bus A0:7 Bus A0:7 Data to Bus B0:7 High Z State on A0:7, B0:7 OE2 L L H
Inputs T/R2 L H X Outputs O tp ts Bus B8:15 Data to Bus A8:15 Bus A8:15 Data to Bus B8:15 High Z State on A8:15, B8:15
H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable
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74VCXH16245
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI VO Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Value -0.5 to +4.6 -0.5 VI +4.6 -0.5 VO +4.6 -0.5 VO VCC + 0.5 IIK IOK DC Input Diode Current DC Output Diode Current -50 -50 +50 IO ICC IGND TSTG DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current Per Ground Pin Storage Temperature Range 50 100 100 -65 to +150 Output in 3-State Note 1.; Outputs Active VI < GND VO < GND VO > VCC Condition Unit V V V V mA mA mA mA mA mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. 1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO IOH IOL IOH IOL IOH IOL TA Dt/DV Supply Voltage Input Voltage Output Voltage HIGH Level Output Current, VCC = 3.0 V - 3.6 V LOW Level Output Current, VCC = 3.0 V - 3.6 V HIGH Level Output Current, VCC = 2.3 V - 2.7 V LOW Level Output Current, VCC = 2.3 V - 2.7 V HIGH Level Output Current, VCC = 1.65 - 1.95 V LOW Level Output Current, VCC = 1.65 - 1.95 V Operating Free-Air Temperature Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V -40 0 (Active State) (3-State) Parameter Operating Data Retention Only Min 1.65 1.2 -0.3 0 0 Typ 3.3 3.3 Max 3.6 3.6 3.6 VCC 3.6 -24 24 -18 18 -6 6 +85 10 Unit V V V mA mA mA mA mA mA C ns/V
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74VCXH16245
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C Symbol VIH Characteristic HIGH Level Input Voltage (Note 2.) Condition 1.65 V VCC < 2.3 V 2.3 V VCC 2.7 V 2.7 V < VCC 3.6 V VIL LOW Level Input Voltage (Note 2.) 1.65 V VCC < 2.3 V 2.3 V VCC 2.7 V 2.7 V < VCC 3.6 V VOH HIGH Level Output Voltage 1.65 V VCC 3.6 V; IOH = -100mA VCC = 1.65 V; IOH = -6mA VCC = 2.3 V; IOH = -6mA VCC = 2.3 V; IOH = -12mA VCC = 2.3 V; IOH = -18mA VCC = 2.7 V; IOH = -12mA VCC = 3.0 V; IOH = -18mA VCC = 3.0 V; IOH = -24mA VOL LOW Level Output Voltage 1.65 V VCC 3.6 V; IOL = 100mA VCC = 1.65 V; IOL = 6mA VCC = 2.3 V; IOL = 12mA VCC = 2.3 V; IOL = 18mA VCC = 2.7 V; IOL = 12mA VCC = 3.0 V; IOL = 18mA VCC = 3.0 V; IOL = 24mA II II(HOLD) ( ) Input Leakage Current Minimum Bushold Input Current 1.65 V VCC 3.6 V; 0V VI 3.6 V VCC = 3.0 V, VIN = 0.8V VCC = 3.0 V, VIN = 2.0V VCC = 2.3 V, VIN = 0.7V VCC = 2.3 V, VIN = 1.6V VCC = 1.65 V, VIN = 0.57V VCC = 1.65 V, VIN = 1.07V II ( ) (OD) Minimum Bushold Over-Drive Current N d d t Ch C t Needed to Change St t State VCC = 3.6 V, (Note 3.) VCC = 3.6 V, (Note 4.) VCC = 2.7 V, (Note 3.) VCC = 2.7 V, (Note 4.) VCC = 1.95 V, (Note 3.) VCC = 1.95 V, (Note 4.) IOZ IOFF ICC DICC 2. 3. 4. 5. 3-State Output Current Power-Off Leakage Current Quiescent Supply Current (Note 5.) 1.65 V VCC 3.6 V; 0 V VO 3.6 V; VI = VIH or VIL VCC = 0 V; VI or VO = 3.6 V 1.65 V VCC 3.6 V; VI = GND or VCC 1.65 V VCC 3.6 V; 3.6 V VI, VO 3.6 V Increase in ICC per Input 2.7 V < VCC 3.6 V; VIH = VCC - 0.6 V These values of VI are used to test DC electrical characteristics only. An external driver must source at least the specified current to switch from LOW-to-HIGH. An external driver must source at least the specified current to switch from HIGH-to-LOW. Outputs disabled or 3-state only. 75 -75 45 -45 25 -25 450 -450 300 -300 200 -200 10 10 20 20 750 mA mA mA mA mA mA VCC - 0.2 1.25 2.0 1.8 1.7 2.2 2.4 2.2 0.2 0.3 0.4 0.6 0.4 0.4 0.55 5.0 mA mA V Min 0.65 x VCC 1.6 2.0 0.35 x VCC 0.7 0.8 V V Max Unit V
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74VCXH16245
AC CHARACTERISTICS (Note 6.; tR = tF = 2.0ns; CL = 30pF; RL = 500W)
Limits TA = -40C to +85C VCC = 3.0 V to 3.6 V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay Input to Output Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output-to-Output Skew (Note 7.) Waveform 1 2 2 Min 0.8 0.8 0.8 0.8 0.8 0.8 Max 2.5 2.5 3.8 3.8 3.7 3.7 0.5 0.5 VCC = 2.3 V to 2.7 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.0 3.0 4.9 4.9 4.2 4.2 0.5 0.5 VCC = 1.65 to1.95 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.0 6.0 9.3 9.3 7.6 7.6 0.75 0.75 Unit ns ns ns ns
6. For CL = 50pF, add approximately 300ps to the AC maximum specification. 7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25C Symbol VOLP Characteristic Dynamic LOW Peak Voltage (Note 8.) Condition VCC = 1.8 V, CL = 30pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30pF, VIH = VCC, VIL = 0 V VOLV Dynamic LOW Valley Voltage (Note 8.) VCC = 1.8 V, CL = 30pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30pF, VIH = VCC, VIL = 0 V VOHV Dynamic HIGH Valley Voltage (Note 9.) VCC = 1.8 V, CL = 30pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30pF, VIH = VCC, VIL = 0 V Typ 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 V V Unit V
8. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH-to-LOW or LOW-to-HIGH. The remaining output is measured in the LOW state. 9. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH-to-LOW or LOW-to-HIGH. The remaining output is measured in the HIGH state.
CAPACITIVE CHARACTERISTICS
Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Condition Note 10. Note 10. Note 10., 10MHz Typical 6 7 20 Unit pF pF pF
10. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC.
AC CHARACTERISTICS (tR = tF = 2.0ns; CL = 50pF; RL = 500W)
Limits TA = -40C to +85C VCC = 3.0 V to 3.6 V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Propagation Delay Input to Output Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output-to-Output Skew (Note 11.) Parameter Waveform 3 4 4 Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.0 3.0 4.4 4.4 4.1 4.1 0.5 0.5 VCC = 2.7 V Min Max 3.6 3.6 5.4 5.4 4.6 4.6 0.5 0.5 Unit ns ns ns ns
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
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74VCXH16245
VIH An, Bn Vm tPLH Bn, An Vm WAVEFORM 1 - PROPAGATION DELAYS tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns VIH OEn, T/Rn tPZH An, Bn Vm Vm tPHZ Vm 0V VOH Vy 0V tPZL An, Bn Vm tPLZ VCC Vx VOL Vm tPHL Vm VOL 0V VOH
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 4. AC Waveforms
VCC Symbol VIH Vm Vx Vy 3.3 V 0.3 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V VCC RL CL RL 6V or VCC x 2 OPEN GND 2.5V 0.2 V VCC VCC/2 VOL + 0.15 V VOH - 0.15 V 1.8 V 0.15 V VCC VCC/2 VOL + 0.15 V VOH - 0.15 V
PULSE GENERATOR RT
DUT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6 V at VCC = 3.3 0.3 V; VCCx 2 at VCC = 2.5 0.2 V; 1.8 V 0.15 V GND
CL = 30pF or equivalent (Includes jig and probe capacitance) RL = 500W or equivalent RT = ZOUT of pulse generator (typically 50W)
Figure 5. Test Circuit
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74VCXH16245
VIH An, Bn Vm tPLH Bn, An Vm WAVEFORM 3 - PROPAGATION DELAYS tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns VIH OEn, T/Rn tPZH An, Bn Vm Vm tPHZ Vm 0V VOH Vy 0V tPZL An, Bn Vm tPLZ VCC Vx VOL Vm tPHL Vm VOL 0V VOH
WAVEFORM 4 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 6. AC Waveforms
VCC Symbol VIH Vm Vx Vy 3.3V 0.3 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V VCC RL CL RL 6V or VCC x 2 OPEN GND 2.7 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V
PULSE GENERATOR RT
DUT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6 V at VCC = 3.3 0.3V; VCC x 2 at VCC = 2.5 0.2 V; 1.8 0.15 V GND
CL = 50pF or equivalent (Includes jig and probe capacitance) RL = 500W or equivalent RT = ZOUT of pulse generator (typically 50W)
Figure 7. Test Circuit
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74VCXH16245
PACKAGE DIMENSIONS
TSSOP DT SUFFIX CASE 1201-01 ISSUE A
48X
K REF 0.12 (0.005)
M
J J1
48 25
M
SECTION N-N L B -U- N
1 24
0.254 (0.010)
PIN 1 IDENT.
A -V-
N F DETAIL E M 0.25 (0.010)
D 0.076 (0.003) -T- SEATING
PLANE
C DETAIL E G H
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCC EEE CCC EEE CCC
TU
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V
S
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 --- 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 --- 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 --- 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 --- 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_
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74VCXH16245/D

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